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em4 7e m 32 8 8sba may. 201 2 1 / 37 www.eorex.com 8g b (32 m 8 bank 32 ) double data rate 3 stack sdram features ? jedec standard vdd/vddq = 1. 5 v 0. 075 v . ? all inputs and outputs are compatible with sstl_1 5 interface. ? fully differential clock inputs (ck, /ck) operation. ? eight banks ? posted cas by pr ogrammable additive latency ? b ust length: 4 with burst chop (bc) and 8. ? cas write latency (c w l): 5, 6,7 ,8 ? cas latency ( c l ): 5, 6, 7,8,9 ,10 ? write latency (wl) =read latency (rl) - 1. ? bi - directional differential data strobe (dqs). ? data inputs on dqs centers when write. ? data outputs on dqs, / dqs edges when read. ? on chip dll align dq, dqs and /dqs transition with ck transition. ? dm mask write data - in at the both rising and falling edges of the data strobe. ? sequen tial & interleaved burst type available both for 8 & 4 with bc. ? multi purpose register (mpr) for pre - defined pattern read out ? on die termination (odt) options: synchronous odt, d yn am ic odt, and asynchronous odt ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms ? refre sh interval: 7.8us t case between 0 c ~ 85 c ? refresh interval: 3 . 9 us t case between 85 c ~ 9 5 c ? rohs compliance ? driver strength:rzq/7, rzq/6 (rzq=240 ) ? high temperature self - refresh rate enable ? zq calibration for dq drive and odt ? reset pin for in itialization and reset function description the em4 7 e m 3288 sba is a high speed stack multi - chip package integrated 4 gbits x 2 ddr3 sdram and fabricated with ultra high performance cmos process containing 8 g bits which organized as 32 mbits x 8 banks by 32 bi ts. this synchronous device achieves high speed double - data - rate transfer rates of up to 1 600 mb/sec/pin (ddr 3 - 1 600 ) for general applications. the chip is designed to co mply with the following key ddr 3 sdram features: (1) posted cas with additive latency, (2) write latency = read latency - 1, (3) on die termination (4) programmable driver strength data ,(5) seamless bl4 access . all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and /ck falling). all i/os are synchronized with a pair of bidirectional differential data strobes (dqs and /dqs) in a source synchronous fashion. the address bus is used to convey row, column and bank addr ess information in a /ras and /cas multiplexing style. the 8 gb ddr 3 devices operates with a single power supply: 1. 5 v 0. 075 v vdd and vddq. available package with rohs compliance : fbga - 1 36 ball (14 x 1 2 x 1.4 mm)
em4 7e m 32 8 8sba may. 201 2 2 / 37 www.eorex.com ordering information part no organizat ion max. freq package grade em4 7e m 32 8 8sba - 150 256 m x 32 ddr3 - 1333h (9 - 9 - 9) fbga - 136 b commercial em4 7e m 32 8 8sba - 125 256 m x 32 ddr3 - 1600k (11 - 11 - 11) fbga - 136 b commercial note: speed ( t ck *) is in order of cl - t rcd - t parts naming rule rp eorex memory ddr3 sdram density organization em 47 em 32 8 8 s b a - x e bm: 32 mega refresh bank interface package revision min cycle time (max freq.) grade am: 16 mega em: 256 mega 16: x16 8: 8k 8: 8bank s: 1.5v b: bga a: 1st -125: 1.25ns, 800mhz (ddr3-1600) : commercial temp. cm: 64 mega -150: 1.5ns, 667mhz (ddr3-1333) dm: 128 mega 08: x8 32: x32 * eorex reserves the right to change products or specification without notice.
em4 7e m 32 8 8sba may. 201 2 3 / 37 www.eorex.com ball assignment : top view 1 2 3 4 9 10 1 1 1 2 vdd vss vssq dq1 a dq9 vssq vss v dd vdd q dq 0 vssq d q 3 b dq11 vssq dq8 v ddq vddq dq2 vssq dm0 c dm1 vssq d q10 vddq vssq vddq d q s0 / dqs 0 d / dqs 1 dq s1 vddq vssq vss q dq 4 vddq dq5 e dq1 3 vddq dq 12 vssq vss dq 6 vddq dq7 f dq 15 vddq dq 14 vss vdd nc cas ras g ck ck cke v dd reset ba2 odt cs h a10 a14 nc nc vrefdq vss zq0 we j a1 zq1 vss vrefca ba0 a9 a2 a0 k a4 a6 a12/ bc ba1 vdd a7 a5 a3 l a8 a11 a13 vdd vss dq24 vddq dq25 m dq17 v ddq dq16 vss vss q dq26 vddq dq27 n dq1 9 vddq dq18 vssq vssq vddq dqs3 /dqs3 p / d qs2 dqs2 vddq vss q vddq dq28 vssq dm3 r dm2 vssq dq20 vddq vddq dq30 vssq dq29 t dq21 vssq dq22 v ddq vdd vss vssq dq31 u dq23 vssq vss vdd 1 36 ball fbga
em4 7e m 32 8 8sba may. 201 2 4 / 37 www.eorex.com ball description (simplified) pin name function g9 , g10 ck, ck (system clock) ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . outp ut (read) data is referenced to the crossings of ck and ck (both directions of crossing). h4 cs (chip select) all commands are masked when cs is registered high. cs provid es for external rank selection on systems with multiple ranks. cs is considered part of the command code. g11 cke (clock enable) cke high activates and cke low deactivates internal clock signals and device input buffers and output dr ivers. taking cke low provides p recharge p ower - d own and s elf - r efresh operation (all banks idle), or a ctive p ower - d own (row a ctive in any bank). cke is asynchronous for self refresh exit. after vrefca has become stable during the power on and initializatio n sequence, it must be maintained during all operations (including s elf - r efresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power - down. input buffers , excluding cke, are disabled during s elf - r efresh. k4 , j 9 , k 3 , l4, k9 , l3 , k 10, l 2 , l9, k2 , h9 , l10 , k11 , l11 , h10 a0~ a9,a10/ap, a11,a12( bc ), a1 3 , a14 (address) provided the row address (ra0 ? ra1 4 ) for a ctive commands and the column address (ca0 - ca9) and a uto p recharge bit for r ead/ w rite commands to select one location out of the memory array in the respective bank. a10 is sampled during a p recharge command to determine whether the p recharge applies to one bank (a10 low) or all banks (a10 hig h). the address inputs also provide the op - code during mode register set commands. a12 is sampled during r ead and w rite commands to determine if burst chop (on - the - fly) will be performed. (high : no burst chop, low : burst chopped). see command truth table f or details. k1 , k12 , h 2 ba0, ba1 ,ba2 (bank address) ba0 ? ba 2 define to which bank an a ctive, r ead, w rite or p recharge command i s being applied . bank address also determines if the mode register is to be accessed during a mrs cycle. h3 odt ( on die termina tion ) odt (registered high) enables termination resistance internal to the ddr 3 sdram. when enabl ed, odt is applied to each dq, dqs , dqs , dm u and dml signal. the odt pin will be ignored if the mode register mr1 is programmed to disable odt.
em4 7e m 32 8 8sba may. 201 2 5 / 37 www.eorex.com ball descript ion ( continued ) d3 , d 10 , p10 , p3 d 4, d9 , p9 , p4 dqs 0~3, /dqs0~3 (data strobe) o utput with read data, input with write data. edge aligned with read data, centered with write data. the data strobes dqs are paired with differential signals /dqs, respectively, to provide di fferential pair signaling to the system during both reads and writes. ddr3 sdram supports differential data strobe only and does not support single - ended. g 4 , g 3 , j4 ras , cas , we (command inputs) ras , cas & we (along with cs ) define the command being entered. c4 ,c 9 , r9 , r4 dm 0 ~md3 ( input data mask) dm is input mask signal for write data. input data is masked when dm are sampled high coinci dent with that input data during a w rite access. dm is sampled on both edges of dqs. b2 , a4,c2 , b4 , e2 , e4 , f2 , f 4,b11,a9,c11,b9,e11,e9 ,f11,f9,m11,m9,n11,n9, r11,t9,t11,u9,m2,m4,n 2,n4,r2,t4,t2,u4 dq0~ 31 (data input/outpu t) data inputs and outputs are on the same pin. a1 , g1 , l1, u1 ,a 12, g12 , l12 , u12 , / f 1 , m1, a 2 , j2 , u2 , a11 , j11 , u11 , f12 , m12 vdd / vss (power supply/ground) vdd and vss are power supply for internal circuits. b1 , c1,r1 , t1 , d2,p2,e3,f 3,m3,n3,e10,f10,m10,n 10,d11,p11, b12,c12,r1 2,t12 / d1 , e1,n1,p1,a3,b 3,c3,r3,t3,u3, a10,b10,c10,r10,t10,u 10,d12,e12,n12,p12 vddq / vssq (dq power supply/dq ground) vddq and vssq are power supply for the output buffers. j 3 , j10 zq 0~ 1 ( zq calibration ) reference pin for zq calibration h1 reset ( active low asynchronous reset ) reset is active when reset is low, and inactive when reset i s high. reset must be high during normal operation. reset is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd, i.e. 1.20v for dc high and 0.30v for dc low. j 1 vref dq (reference voltage) r eference voltage for dq j12 vref ca (reference voltage) r eference voltage for ca g2 , h11 , h 12 nc (no connection) no i nternal electrical connection is present. note: input pins only ba0 - ba2, a0 - a13, ras , cas , we , cs , cke, odt and reset do not supply termination.
em4 7e m 32 8 8sba may. 201 2 6 / 37 www.eorex.com absolute maximum rating symbol item rating units v in , v out input, output voltage - 0. 4 ~ + 1.975 v v dd power supply voltage - 0 . 4 ~ + 1.975 v v ddq power supply voltage - 0. 4 ~ + 1.975 v t op operating temperature range commercial 0 ~ +70 c t stg storage temperature range - 55 ~ +1 0 0 c v reference voltage for control refca - 0.4 ~ 0.6*vdd v v reference voltage for dq refdq - 0.4 ~ 0.6*vddq v note: caution exposing the device to stress above those listed in absolute maximum ratin gs could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. recommended dc operating conditions symbol parameter min. typ. max. units v dd p ower supply voltage 1. 425 1. 5 1. 575 v v ddq power supply for i/o voltage 1. 425 1. 5 1. 575 v single - ended ac and dc input levels for command and address symbol parameter min. max. units v ihca (dc100) dc input logic high vref+0.100 vdd v v ilca (d c100) dc input logic low vss vref - 0.100 v v ihca (ac175) ac input logic high vref+0.175 - v v ilca (ac175) ac input logic low - vref - 0.175 v v ihca (ac150) ac input logic high vref+0.150 - v v ilca (ac150) ac input logic low - vref - 0.150 v v refca (dc ) reference voltage for add, cmd 0.49*vdd 0.51*vdd v single - ended ac and dc inpu t levels for dq and dm symbol parameter min. max. units v ihdq (dc100) dc input logic high vref+0.100 vdd v v il dq (dc100) dc input logic low vss vref - 0.100 v v ihdq ( ac175) ac input logic high vref+0.150 - v v ildq (ac175) ac input logic low - vref - 0.150 v v ihdq (ac150) ac input logic high vref+0.150 - v v il dq (ac150) ac input logic low - vref - 0.150 v v refdq (dc) reference voltage for dq, dm 0.49*vdd 0.51*vdd v note 1. for input pins except /reset: vref= v refca (dc) or vref= v refdq (dc). note2. the ac peak noise on vref may not allow vref to deviate from v refca (dc) or vref= v refdq (dc) by more than 1% vdd (for reference: approx. 15mv. note3. for reference voltage = vdd/2 15mv.
em4 7e m 32 8 8sba may. 201 2 7 / 37 www.eorex.com pin capacitance symbol parameters pins min. max. unit notes cck input pin capacitance, ck, /ck ck, /ck 0.8 1.4 pf 1,3 cdck delta input pin capacitance, ck, /ck 0 0.15 pf 1,2 cin_ctrl input pin capacitance, control pins /cs,cke,od t 0.75 1.3 pf 1 cdin_ctrl delta input pin capacitance, control pins - 0.4 0.2 pf 1,4 cin_add_cmd input pin capacitance, address and command pins /ras,/cas,/we, address 0.75 1.3 pf 1 cdin_add_cmd delta input pin capacitance, address and command pins - 0. 4 0.4 pf 1,5 cio input/output pins capacitance dq,dqsu,/dqsu dqsl,/dqsl, dmu, dml 1.5 2.5 pf 1 ,6 cdio delta input/output pins capacitance - 0.5 0.3 pf 1,7,8 cddqs delta input/output pins capacitance dqs, /dqs 0 0.15 pf 1,10 czq input/output pin capacit ance, zq zq - 3 pf 1,9 notes1. vdd, vddq, vss, vssq applied and all other pins (except the pin under test) floating. vdd = vddq =1.5v, vbias=vdd/2. notes2. absolute value of cck(ck - pin) - cck(/ck - pin). notes3 . cck (min.) will be equal to cin (min.) notes4 . cdin_ctrl = cin_ctrl - 0.5 * (cck(ck - pin) + cck(/ck - pin)) notes5 . cdin_add_cmd = cin_add_cmd - 0.5 * (cck(ck - pin) + cck(/ck - pin)) notes6. although the dm u and dml pin s ha ve different functions, the loading matches dq and dqs. notes7. dq should be in high imp edance state. notes8. cdio = cio (dq, dm) - 0.5 * (cio(dqs - pin) + cio(/dqs - pin)). notes9. maximum external load capacitance on zq pin is 5pf. notes10. absolute value of cio(dqs) - cio(/dqs).
em4 7e m 32 8 8sba may. 201 2 8 / 37 www.eorex.com ac and dc logic input levels for differential signals differentia l signals definition differential ac and dc input levels symbol parameter min. max. units note v ihdiff differential input high +0.2 s ee note3 v 1 v ildiff differential input low s ee note3 - 0.2 v 1 v ihdiff (ac) ac differential input high 2x(vih( ac) - vref) s ee note3 v 2 v ildiff (ac) ac differential input low s ee note3 2x( vil(ac) - vref) v 2 note1. it is u sed to define a differential signal slew - rate. note 2 . f or ck - / ck use vih/vil(ac) of address/command and vrefca; for strobes (dqs, dqs) use vih /vil(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. note 3 . these values are not defined, however they single - ended signals ck, / ck, dqs, / dqs need to be within the respectiv e limits (vih(dc) max, vil(dc)min) for single - ended signals.
em4 7e m 32 8 8sba may. 201 2 9 / 37 www.eorex.com differential swing requirements for clock (ck - / ck) and strobe (dqs - / dqs ) - allowed time before ringback (tdvac) for ck - /ck and dqs - /dqs slew rate [v/ns] tdvac [ps] @ |vih/ldiff(ac)| = 35 0mv tdvac [ps] @ |vih/ldiff(ac)| = 300mv - min max min max >4.0 75 - 175 - 4 .0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - <1.0 0 - 150 - single - ended requirements for diffe rential signals each individual component of a differential signal (ck, dqs, / ck, / dqs) has also to comply with certain requirements for single - ended signals. ck and / ck have to approximately reach vsehmin / vselmax (approximately equal to the ac - levels (v ih( ac ) / vil( ac ) ) for a ddress /c ommand signals) in every half - cycle. dqs, / dqs have to reach vsehmin / vselmax [ approximately the ac - levels (vih( ac ) / vil( ac ) ) for dq signals ] in every half - cycle preceding and following a valid transition. note that the a pplicab le ac - levels for a ddress /c ommand and dq?s might be different per speed - bin etc. e.g., if v ihca (ac150)/v il ca (ac150) is used f or a ddress /c ommand signals, then these ac - levels apply also for the single - ended components of differential ck and / ck .
em4 7e m 32 8 8sba may. 201 2 10/ 37 www.eorex.com note that while address/command and dq signal requirements are with respect to vref, the single - ended components of differential signals have a requirement with respect to vdd/2; this is nominally the same. the transition of single - ended signals through th e ac - levels is used to measure setup time. for singleended components of differential signals the requirement to reach vsel max, vseh min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. single - ended lev els for ck, dqs, /ck, /dqs symbol parameter min. max. units note vseh single - ended high - level for strobes (vdd/2)+0.175 s ee note3 v 1,2 single - ended high - level for ck, /ck (vdd/2)+0.175 s ee note3 v 1,2 vsel single - ended low - level for strobes s ee note3 (vdd/2) - 0.175 v 1, 2 single - ended low - level for ck, /ck s ee note3 (vdd/2) - 0.175 v 1, 2 note1. for ck, / ck use vih/vil(ac) of address/command; for strobes (dqs, dqs) use vih/vil(ac) of dqs. note2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac )/vil(ac) for address/command is based on vrefca; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. note3. these values are not defined, however the single - ended components of differential signals ck , / ck, dqs, / dqs need to be within the respective limits (vih(dc) max, vil(dc) min) for single - ended signals as well as the limitations for overshoot and undershoot.
em4 7e m 32 8 8sba may. 201 2 11 / 37 www.eorex.com ac and dc output measure ment levels symbol parameter specification units note v oh (dc) dc output high measurement level (for iv curve linearity) 0.8*v v ddq v om (dc) dc output middle measurement level (for iv curve linearity) 0.5 *v v ddq v ol (dc) dc output low measurement level (for iv curve linearity) 0. 2 *v v ddq v oh ( a c) a c output high measurement level (for output slew rate) vtt+ 0. 1 *v v ddq 1 v ol (a c) ac output low measurement level (for output slew rate) vtt - 0. 1 *v v ddq 1 v ohdiff (dc) ac differential output high measurement level (for output slew rate) 0.2*v v ddq 2 v oldiff (dc) ac diff erential output low measurement level (for output slew rate) - 0.2*v v ddq 2 notes 1. the swing of 0.1 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 34 and an effective test load of 25 to vtt = vddq/2 at each of the differential outputs. notes 2. the swing of 0.2 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 34 and an effective test load of 25 to vtt = vddq/2 at each of the differential outputs. dqs output crossing voltage - vox (ddr3 - 1600 or higher speed bin) symbol parameters dqs, /dqs differential slew rate unit 5v/ns 6v/ns 7v/ns 8v/ns 9v/ns 10v/ns 11v/ns 12v/ns v ox deviation of dqs, /dqs output cros s point voltage from 0.5*v (ac) max. +100 ddq +120 +140 +160 +180 +200 +200 +200 mv v ox - 100 (ac) min. - 120 - 140 - 160 - 180 - 200 - 200 - 200 mv dqs output crossing voltage - vox (ddr3 - 1 333 or low er speed bin) symbol parameters dqs, /dqs differential slew rate unit 5v/ns 6v/ns 7v/ns 8v/ns 9v/ns 10v/ns 11v/ns 12v/ns v ox deviation of dqs, /dqs output cross point voltage from 0.5*v (ac) max. +125 ddq +1 5 0 +175 +20 0 +225 +2 25 +2 25 +2 25 mv v ox - 1 25 (ac) min. - 1 5 0 - 1 75 - 200 - 225 - 2 25 - 2 25 - 2 25 mv notes1. measured usin g an effective test load of 25 to 0.5 * v ddq at each of the differential outputs. notes2. for a differential slew rate in between the listed values, the v ox value may be obtained by linear interpolation. notes3. the dqs, /dqs pins under test are not requir ed to be able to drive each of the slew rates listed in the table; the pins under test will provide one v ox value when tested with specified test condition. the dqs and /dqs differential slew rate when measuring v ox determines which v ox limits to use.
em4 7e m 32 8 8sba may. 201 2 12/ 37 www.eorex.com re commended dc operating conditions (v dd ,v ddq = 1 . 5 v0. 075 v) symbol parameter & test conditions - 1 2 5 - 1 50 units max i dd1 operating one bank active - read - precharge current : cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see timing used table; bl: 81; al: 0; / cs: high between act, rd and pre; command, address, data io: partially toggling; dm:stable at 0; bank activity: cycling with one bank active at a time; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 tbd tbd ma i d d2p 1 precharge power - down current fast exit : cke: low; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; / cs: stable at 1; command, address: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer an d rtt: enabled in mode registers; odt signal: stable at 0; pre - charge power down mode: fast exit tbd tbd ma i dd2n precharge standby current : cke: high; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; / cs: stable at 1; command, address: p artially toggling; data io: floating; dm:stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 tbd tbd ma i dd3p active power - down c urrent : cke: low; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; / cs: stable at 1; command, address: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 tbd tbd ma i dd4 w operating burst write current : cke: high; external clock: on; tck, cl: see timing used table; bl: 8; al: 0; / cs: high between wr; command, address: partially toggling; data io: seamless write data burst with different data between one burst and the next one; dm: stable at 0; b ank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers; odt signal: stable at high tbd tbd ma i dd4 r operating burst read current : cke: high; external clock: on; tck, cl: see timi ng used table; bl: 8; al: 0; / cs: high between rd; command, address: par - tially toggling; data io: seamless read data burst with different data between one burst and the next one; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 tbd tbd ma i dd5 b burst refresh current : cke: high; external clock: on; tck, cl, nrfc: see timing used table; bl: 8; al: 0; / cs: high between ref; command, a ddress: partially toggling; data io: floating; dm: stable at 0; bank activity: ref command every nrfc; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 tbd tbd ma
em4 7e m 32 8 8sba may. 201 2 13/ 37 www.eorex.com symbol parameter & test conditions - 1 2 5 - 1 50 units max i dd6 self refresh current: normal temperature range; tcase: 0 - 85c; auto self - refresh (asr): disabled; self - refresh t emperature range (srt): normal; cke: low; external clock: off; ck and / ck: low; cl: see timing used table; bl: 8; al: 0; cs, command, address, data io: floating; dm: stable at 0; bank activity: self - refresh operation; output buffer and rtt: enabled in mode registers; odt signal: floating tbd tbd ma i dd7 operating bank interleave read current; cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see timing used table; bl: 8; al: cl - 1; cs: high between act and rda; command, address: partially toggling; data io: read data bursts with different data between one burst and the next one; dm: stable at 0; bank activity: two times interle aved cycling through banks (0, 1, ...7) with different addressing; output buffer and rtt: enabled in mode registers; odt signal: stable at 0 tbd tbd ma note 1: burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b note 2 : output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b note 3 : precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit note 4 : auto self - refresh (asr): set mr2 a6 = 0b to disabl e or 1b to enable feature note 5 : self - refresh temperature range (srt): set mr2 a7=0b for normal or 1b for extended temperature range note 6 : refer to dram supplier data sheet and/or dimm spd to determine if optional features or requirements are supported by ddr3 sdram note 7 : read burst type: nibble sequential, set mr0 a[3]=0b
em4 7e m 32 8 8sba may. 201 2 14/ 37 www.eorex.com block diagram r o w a d d . b u f f e r r o w d e c o d e r a d d r e s s r e g i s t e r auto / self refresh counter memory array s / a & i / o gating col . decoder col . add . buffer mode register set col add . counter burst counter dqm control data in data out dio a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 ba0 ba1 timing register clk cke / cs / ras / cas / we /reset dm0,dm1,dm2,dm3 /clk odt dqs0~3, /dqs0~3 receiver write fifo driver dqs generator dll clk, /clk clk, /clk ba2 a 13 a 14 zq0, zq1
em4 7e m 32 8 8sba may. 201 2 15/ 37 www.eorex.com ac operating test characteristics ddr3 - 1 333 & ddr3 - 1 600 speed bins (v dd , v ddq = 1 . 5 v0. 075 v ) symbol speed bin - 1 2 5 (ddr3 - 1 600 ) - 150 (ddr3 - 1 333 ) units notes cl - n rcd- nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t aa internal read command to first data 13.125 20 13. 5 20 ns 8 t rcd active to read or write delay 13.125 - 13. 5 - ns 8 t rp precharge command period 13.125 - 13. 5 - ns 8 t rc active to active/aut o refresh command 4 8 .7 5 - 49.5 - ns 8 t ras active to precharge command period 3 5 9*t refi 3 6 9*t refi ns 7 t ck (avg) average clock cycle, cl=6, cwl=5 2.5 3.3 2.5 3.3 ns 1,2,3, 5 .6 t ck (avg) average clock cycle, cl=7, cwl=6 1.875 2.5 1.875 2.5 ns 1,2,3,4 ,5 , 6 t ck (avg) average clock cycle, cl=8, cwl=6 1.875 2.5 1.875 2.5 ns 1,2,3, 5 ,6 t ck (avg) average clock cycle, cl=9, cwl=7 1.5 1.875 1.5 1.875 ns 1,2,3,4 ,6 t ck (avg) average clock cycle, cl=10, cwl=7 1.5 1.875 1.5 1.875 ns 1,2,3, 6 t ck (avg) average clock cycle, cl=11, cwl=8 1.25 1.5 - - ns 1,2,3 - support cl settings 6,7, 8,9 ,10,11 6,7,8,9,10 nck - support cwl settings 5, 6,7 ,8 5,6,7 nck notes1 . the cl setting and cwl setting result in tck (avg) (min.) and tck (avg) (max.) requirements. when making a s election of tck (avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. notes 2 . tck (avg) (min.) limits: since /cas latency is not purely analog - data and strobe output are synchronized by the dll - all pos sible intermediate frequencies may not be guaranteed. an application should use the next smaller jedec standard tck (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating cl (nck) = taa (ns) / tck (avg)(ns), rounding up to the next ?supported cl?. notes 3. tck (avg) (max.) limits: calculate tck (avg) + taa (max.)/cl selected and round the resulting tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). this result is tck (avg) (max.) corresponding to cl selected. notes 4. ?r eserved? settings are not allowed. user must program a different value. notes 5. any ddr3 - 1333 speed bin also supports functional operation at lower frequencies as shown in the table ddr3 - 1333 speed bins which is not subject to production tests but verified by design/characterization. notes 6. any ddr3 - 1600 speed bin also supports functional operation at lower frequencies as shown in the table ddr3 - 1600 speed bins which is not subject to production tests but verified by design/characterization. notes 7. trefi depends on operating case temperature (tc). notes 8. for devices supporting optional down binning to cl = 7 and cl = 9, taa/trcd/trp(min.) must be 13.125 ns or lower. spd settings must be programmed to match.
em4 7e m 32 8 8sba may. 201 2 16/ 37 www.eorex.com ac operating test characteristics (v dd , v ddq = 1 . 5 v0. 075 v ) symbol speed bin - 1 2 5 (ddr3 - 1 600 ) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t ck minmum c lock c ycle, dll - off m ode 8 - 8 - ns 6 t ch , t cl (avg) a verage ck high/low level width 0.47 0.53 0.47 0. 53 ns t rrd active bank a to a ctive bank b command period (1kb page size) 6 - 6 - ns 4 - 4 - nck t faw four activate window 30 - 30 - ns t ih (base) dc100 address and control input hold time (vih/vil(dc100) levels) 120 - 140 - ps 16 t is (base) a c1 75 address and control input setup time (vih/vil(ac175) levels) 4 5 - 6 5 - ps 16 t is (base) a c1 5 0 address and control input setup time (vih/vil(a c1 5 0) levels) 4 5+125 - 6 5+1 2 5 - ps 16,24 t dh (base) dq and dm input hold time (vih/vil(dc ) levels) 4 5 - 65 - ps 17 t ds (base) dq and dm input setup time (vih/vil(ac) levels) 10 - 30 - ps 17 t ipw address and c ontrol input pulse width for each input 5 60 - 620 - ps 25 t dipw dq and dm input pulse width for each input 360 - 400 - ps 25 t hz (dq) dq high impedance time - 2 2 5 - 250 ps 13,14 t lz (dq) dq low impedance time - 4 50 2 2 5 - 5 00 250 ps 13,14 t hz (dqs) dqs,/dqs high impedance time rl+bl/2 reference - 2 2 5 - 250 ps 13,14 t lz (dqs) dqs,/dqs low impedance time rl - 1 reference - 4 50 2 2 5 - 5 00 250 ps 13,14 t dqsq dqs,/dqs to dq s kew per group, per access - 100 - 1 2 5 ps 12,13 t ccd /cas to /cas command delay 4 - 4 - nck t qh dq output hold time from dqs, /dqs 0.38 - 0.38 - t ck (avg) 12,13 t dqsck dqs,/dqs rising edge output access time from rising ck,/ck - 2 2 5 2 2 5 - 255 255 ps 12,13 t dqss dqs latch rising transitions to associated clock edges - 0.2 7 0.2 7 - 0.25 0.25 t ck (avg) t dqsh dqs input high pulse width 0.45 0.55 0.45 0.55 t ck (avg) 27,28
em4 7e m 32 8 8sba may. 201 2 17/ 37 www.eorex.com ac operating test characteristics (v dd , v ddq = 1 . 5 v0. 075 v ) symbol speed bin - 1 2 5 (ddr3 - 1 6 00 ) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t dsh dqs falling edge hold time from rising ck 0. 18 - 0.2 - t ck (avg) 29 t dss dqs falling edge setup time to rising ck 0. 18 - 0.2 - t ck (avg) 29 t dqsl dqs input low pulse width 0.45 0.55 0.45 0.55 t ck (avg) 26,28 t qsh dqs output high time 0.40 - 0. 40 - t ck (avg) 12,13 t qsl dqs output low time 0.40 - 0. 40 - t ck (avg) 12,13 t mrd mode register set command cycle 4 - 4 - nck t mod mode register set command up date delay 15 - 15 - ns 12 - 12 - nck t rpre read preamble time 0.9 - 0.9 - t ck (avg) 13,19 t rpst read postamble time 0.3 - 0.3 - t ck (avg) 11,13 t wpre write preamble time 0.9 - 0.9 - t ck (avg) 1 t wpst write postamble time 0.3 - 0.3 - t ck (avg) 1 t wr write recovery time 15 - 15 - ns t dal (min) auto precharge write recovery + precharge time wr + roundup[trp / tck(avg) ] nck t mprr multi purpose register recovery time 1 - 1 - nck 22 t wtr internal write to read command delay 7.5 - 7.5 - ns 18 4 - 4 - nck t rtp internal read to precharge command delay 7.5 - 7.5 - ns 4 - 4 - nck t ckesr minimum cke low width for self - refresh entry to exit t cke (min) +1 - t cke (min) +1 - nck t cksre valid clock requirement after self - refresh entry or power - d own entry 10 - 10 - ns 5 - 5 - nck t cksrx valid clock requirement before self - refresh exit or power - down exit 10 - 10 - ns 5 - 5 - nck
em4 7e m 32 8 8sba may. 201 2 18/ 37 www.eorex.com ac operating test characteristics (v dd , v ddq = 1 . 5 v0. 075 v ) symbol speed bin - 1 2 5 (ddr3 - 1 600 ) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t xs exit self - refresh to command s not requiring a locked dll t rfc (min) + 10 - t rfc (min) + 10 - ns 5 - 5 - nck t x s dll exit s elf - refresh to command s requiring a locked dll t dll (min) - t dll (min) - nck t rfc auto - refresh to a ctive/ a uto - refresh command 160 - 160 - ns t refi average periodic refresh interval 0 Qt c Q +85 - 7.8 - 7.8 s t refi average periodic refresh interval +85 Qt c Q+ 9 5 - 3.9 - 3.9 s t cke cke minimum high and low pulse width 5 - 5.625 - ns 3 - 3 - nck t xpr exit reset from cke high to a valid command t rfc (min) + 10 - t rfc (min) + 10 - n s 5 - 5 - nck t dllk dll locking time 512 - 512 - nck t pd power - down entry to exit time t cke (min) 9*t refi t cke (min) 9*t refi 15 t xpdll exit precharge power - down with dll frozen to command s requiring a locked dll 24 - 2 4 - ns 2 10 - 10 - nck t x p exit power - down with dll on to any valid command; exit precharge power - down with dll frozen to commands not requiring a locked dll 6 - 6 - ns 3 - 3 - nck t wrpden (min) timing of wr command to power - down entry (bl8otf, bl8mrs, bl4otf) w l + 4 + [t w r / tck(avg) ] nck 9 t wrpden (min) timing of wr command to power - down entry (bc4mrs) wl + 2 + [twr / tck(avg)] nck t wrapden timing of wr a command to power - down entry (bl8otf, bl8mrs, bl4otf) wl + 4 + wr + 1 - wl + 4 + wr + 1 - nck 10 t wrapden timing of wr a command to power - down entry (bc4mrs) wl + 2 + wr + 1 - wl + 2 + wr + 1 - nck 10
em4 7e m 32 8 8sba may. 201 2 19/ 37 www.eorex.com ac operating test characteristics (v dd , v ddq = 1 . 5 v0. 075 v ) symbol speed bin - 1 2 5 (ddr3 - 1 600 ) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t refpden timing of ref command to power - down entry 1 - 1 - nck 2 0,2 1 t mrspden timing of mrs command to power - down entry t mod (min) - t mod (min) - t cpded command pass disable delay 1 - 1 - nck t actpden timing of act command to power - down entry 1 - 1 - nck 20 t prpden timing of pre command to power - down entry 1 - 1 - nck 20 t rdpden timing of rd/rda command to power - down entry rl + 4 +1 - rl + 4 + 1 - nck t aon rtt turn - on - 2 2 5 2 2 5 - 250 250 p s 7 t aonpd asynchronous rtt turn - on delay (power - down with dll frozen) 2 8.5 2 8.5 ns t aof rtt_nom and rtt_wr turn - off time from odtloff reference 0.3 0.7 0.3 0.7 t ck (avg) 8 t aofpd asynchronous rtt turn - off delay (power - down with dll frozen) 2 8.5 2 8.5 ns odth4 odt high time withou t write command or with write command and bc4 4 - 4 - nck odth8 odt high time with write command and bl8 6 - 6 - nck t adc rtt dynamic change skew 0.3 0.7 0.3 0.7 t ck (avg) t zqinit power - up and reset calibration time 512 - 512 - nck t zqoper normal o peration full calibration time 256 - 256 - nck t zqcs normal operation short calibration time 64 - 64 - nck 23 t wlmrd first dqs pulse rising edge after write leveling mode is programmed 40 - 40 - nck 3 t wldqsen dqs./dqs delay after write leveling mode i s programmed 25 - 25 - nck 3 t rtw read to write command delay (bc4mrs, bc4otf) rl + t ccd /2 + 2nck - wl - rl + t ccd /2 + 2nck - w l - t rtw read to write command delay (bl8mrs, bl8otf) rl + t ccd /2 + 2nck - wl - rl + t ccd /2 + 2nck - w l - t rap active to read with auto precharge command delay t rcd min - t rcd min -
em4 7e m 32 8 8sba may. 201 2 20/ 37 www.eorex.com ac operating test characteristics (v dd , v ddq = 1 . 5 v0. 075 v ) symbol speed bin - 1 2 5 (ddr3 - 1 600 ) - 1 50 (ddr3 - 1 333 ) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t wls write le veling setup time from rising ck,/ck crossing to rising dqs,/dqs crossing 165 - 195 - ps t wlh write leveling hold time from rising dqs,/dqs crossing to rising ck,/ck crossing 165 - 195 - ps t wlo write leveling output delay 0 7.5 0 9 ns t wloe write le veling output error 0 2 0 2 ns t ck (abs) absolute clock period t ck (avg) min+ t jit (per)min t ck (avg)max+ t jit (per)max t ck (avg)min+ t jit (per)min t ck (avg)max+ t jit (per)max ps t ch (abs) absolute clock high pulse width 0.43 - 0.43 - t ck (avg) 30 t cl ( abs) absolute clock low pulse width 0.43 - 0.43 - t ck (avg) 31 t jit ( per ) c lock period jitter - 7 0 7 0 - 8 0 8 0 p s t jit ( per,lck ) clock period jitter during dll locking period - 6 0 6 0 - 7 0 7 0 ps t jit ( cc) cycle to cycle period jitter - 140 - 1 6 0 ps t jit ( cc,lck ) cycle to cycle period jitter during dll locking period - 120 - 140 ps t err (2per) cumulative error across 2 cycles - 103 103 - 118 118 ps t err (3per) cumulative error across 3 cycles - 122 1 22 - 1 40 1 40 ps t err (4per) cumulative error across 4 cy cles - 1 36 1 36 - 155 155 ps t err (5per) cumulative error across 5 cycles - 1 47 1 47 - 168 168 ps t err (6per) cumulative error across 6 cycles - 1 55 1 55 - 177 177 ps t err (7per) cumulative error across 7 cycles - 1 63 1 63 - 186 186 ps t err (8per) cumulative e rror across 8 cycles - 1 69 1 69 - 193 193 ps t err (9per) cumulative error across 9 cycles - 175 175 - 2 00 2 00 ps t err (10per) cumulative error across 10 cycles - 180 180 - 2 05 2 05 ps t err (11per) cumulative error across 11 cycles - 184 184 - 2 10 2 10 ps t err (12per) cumulative error across 12 cycles - 188 188 - 2 15 2 15 ps t err (nper) cumulative error across n= 13,14, ? 49,50 cycles t err (nper)min=(1+0.68ln(n))* t jit (per)min t err (nper)max=(1+0.68ln(n))* t jit (per)max ps 32
em4 7e m 32 8 8sba may. 201 2 21/ 37 www.eorex.com ac operating test characteristics (v dd , v ddq = 1 . 5 v0. 075 v ) symbol speed bin - 125 (ddr3 - 1600) - 150 (ddr3 - 1333) units notes cl - nrcd - nrp 11 - 11 - 11 9 - 9 - 9 parameter min. max. min. max. t anpd odt to power - down entry/ exit latency wl ? 1 - wl ? 1 - nck odtl on odt turn on latency wl ? 2 wl ? 2 w l ? 2 wl ? 2 nck odtl off odt turn off latency wl ? 2 wl ? 2 wl ? 2 wl ? 2 nck odtl cnw odt latency for changing from rtt_nom to rtt_wr wl ? 2 wl ? 2 wl ? 2 wl ? 2 nck odtl cwn4 odt latency for changing from rtt_wr to rtt_nom (bc4) - 4+odtl off - 4+odtl off nck odtl cwn8 od t latency for changing from rtt_ wr to rtt_ nom (bl8) - 6 +odtl off - 6 +odtl off nck note 1: actual value dependant upon measurement level definitions which are tbd. note 2: commands requiring a locked dll are: read (and reada) and synchronous odt commands. n ote 3 : the max values are system dependent. no te 4 : wr as programmed in mode register. note 5 : value must be rounded - up to next higher integer value. note 6 : there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. note 7 : odt turn on time (min.) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time (max.) is when the odt resistance is fully on. both are measured from odtlon. note 8 : odt turn - off time (min.) is when the device st arts to turn - off odt resistance. odt turn - off time (max.) is when the bus is in high impedance. both are measured from odtloff. note 9 : twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. note 10 : wr in clock cycles as programmed in mr0. note 1 1 : the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. note 1 2: output timing deratings are relative to the sdram input clock. when the device is operated with input clock jitter, this parameter needs to be derated by tbd. note 13: value is only valid for ron34. note 14: single ended signal parameter. refer to the section of tlz(dqs), tlz(dq), thz(dqs), thz(dq) notes for definition and measurement m ethod. note 15: trefi depends on operating case temperature (tc). note 16: tis(base) and tih(base) values are for 1v/ns command/ addresss single - ended slew rate and 2v/ns ck, / ck differential slew rate, note for dq and dm signals, vref(dc) = vrefdq(dc). fo r input only pins except reset, vref(dc) = vrefca(dc). see address / command setup, hold and derating section. note 17: tds(base) and tdh(base) values are for 1v/ns dq single - ended slew rate and 2v/ns dqs, / dqs differential slew rate. note for dq and dm si gnals, vref(dc)= vrefdq(dc). for input only pins except reset, vref(dc) = vrefca(dc). see data setup, hold and and slew rate derating section.
em4 7e m 32 8 8sba may. 201 2 22/ 3 7 www.eorex.com note 18: start of internal write transaction is defined as follows ; for bl8 (fixed by mrs and on - the - fly , otf ) : rising clock edge 4 clock cycles after wl. for bc4 (on - the - fly , otf ) : rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs) : rising clock edge 2 clock cycles after wl. note 19: the maximum read preamble is bound by tlzdqs(min) on the left si de and tdqsck(max) on the right side. note 20: cke is allowed to be registered low while operations such as row activation, precharge, auto precharge or refresh are in progress, but power - down idd spec will not be applied until finishing those operation. n ote 21: although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. note 22: defined between end of mpr read burst and mrs which reloads m pr or disables mpr function. note 23: one zqcs command can effectively correct a minimum of 0.5 % (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and temperature sensitivity? tables. the appropriate interval between zqcs commands can be determined from these tables and other application specific parameters. one method for calculating the interval between zqc s commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula: ate) x vdriftr (vsens ) tdriftrate x (tsens on zqcorrecti + where tsens = max(drttdt, d rondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. note 24: the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100 ps of derating to accommodate for the low er alternate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. note 25: pulse width of a input signal is defined as the width between the first crossing of vref(dc) and the consecutive crossing o f vref(dc). note 26: tdqsl describes the instantaneous differential input low pulse width on dqs - / dqs, as measured from one falling edge to the next consecutive rising edge. note 27: tdqsh describes the instantaneous differential input high pulse width o n dqs - / dqs, as measured from one rising edge to the next consecutive falling edge. note 28: tdqsh,act + tdqsl,act = 1 tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. note 29: tdsh,act + tdss, act = 1 tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. note 30: tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. n ote 31: tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. note 32: n = from 13 cycles to 50 cycles. this row defines 38 parameters.
em4 7e m 32 8 8sba may. 201 2 23/ 37 www.eorex.com simplified state diagram
em4 7e m 32 8 8sba may. 201 2 24/ 37 www.eorex.com 1. command truth table command symbol cke /cs /ras /cas /we ba0 ~ ba2 a10 a12 , a10 ~a0 n -1 n de vice deselect des h h h x x x x x x ,x no operation nop h h l h h h v v v,v read (fixed bl8/bc4 ) rd h h l h l h ba l v,ca read (bc4 , otf ) rds4 h h l h l h ba l l,ca read (bl8, otf) rds8 h h l h l h ba l h,ca read with auto pre - charge (fixed bl8/bc4) rda h h l h l h ba h v,ca read with auto pre - charge (bc4, otf) rdas4 h h l h l h ba h l,ca read with auto pre - charge (bl8, otf) rdas8 h h l h l h ba h h,ca write (fixed bl8/bc4) wr h h l h l l ba l v,ca write (bc4, otf) wrs4 h h l h l l ba l l,ca write (bl8,otf) wrs8 h h l h l l ba l h,ca write with auto pre - charge (fixed bl8/bc4) wra h h l h l l ba h v,ca write with auto pre - charge (bc4, o tf) wras 4 h h l h l l ba h l,ca write with auto pre - charge (bl8, otf) wras 8 h h l h l l ba h h,ca bank activate act h h l l h h ba ra pre - charge s ingle bank pre h h l l h l ba l v,v pre - charge all banks prea h h l l h l v h v,v mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v,v self r efresh entry sre h l l l l h v v v,v self refresh exit srx l h h x x x x x x,x l h h h v v v,v power down entry pde h l h x x x x x x ,x h l l h h h v v v,v power down exit pd x l h h x x x x x x ,x l h l h h h v v v,v zq calibration long zqcl h h l h h l x h x,x zq calibration short zqcs h h l h h l x l x,x h = high level, l = low level, x = do n't care, v = valid , ba=bank address, ca=column address , ra=row address
em4 7e m 32 8 8sba may. 201 2 25/ 37 www.eorex.com n ote 1 . all ddr3 sdram commands are defined by states of / cs , / ras , / cas, / we and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant. n ote 2 . / reset is l ow enable command which w ill be used only for asynchronous reset so must be maintained high during any function. n ote 3 . bank addresses (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. n ote 4 . ?v? means ?h or l (but a defined logic level)? and ?x? means either ?defined or undefined (like floating) logic level?. n ote 5 . burst reads or writes cannot be terminated or interrupted and fixed/on - the - fly (otf) bl will be defined by mrs. n ote 6 . the power down mode does not perform any refresh operation. n ote 7 . the state of odt does not affect the states described in this table. the odt function is not available during self refresh. n ote 8 . self refresh exit is asynchronous. n ote 9 . vref(both v ref dq and v ref ca) must be maintained during self refr esh operation. v ref dq supply may be turned off and vrefdq may take any value between vss and vdd during self refresh operation, provided that v ref dq is valid and stable prior to cke going back h igh and that first write operation or first write leveling act ivity may not occur earlier than 512 nck after exit from self refresh. n ote1 0 . the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no operation command (nop) is to prevent the ddr3 sdram from registerng any unwanted commands between operations. a no operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle. n ote 11. the deselect command performs the same function as no operation comma nd. n ote 12. refer to the cke truth table for more detail with cke transition.
em4 7e m 32 8 8sba may. 201 2 26/ 37 www.eorex.com 2. cke truth table current state cke command (n) /ras, /cas, /we, /cs action (n) notes n - 1 n power down l l x maintain power down 14,15 l h d eselect or nop p ower down exit 11,14 self refresh l l x maintain self refresh 15,16 l h deselect or nop self refresh exit 8,12,16 bank active h l deselect or nop active power down entry 11,13,14 reading h l deselect or nop power down entry 11,13,14,17 writing h l deselect or nop power down entry 11,13,14,17 precharging h l deselect or nop power down entry 11,13,14,17 refreshing h l deselect or nop precharge power down entry 11 all banks idle h l deselect or nop precharge power down entry 11,13,14,18 h l refresh self refre sh 9,13,18 for more details with all signals, see ? command truth table ? 10 n ote 1 . cke ( n ) is the logic state of cke at clock edge n ; cke ( n - 1) was the state of cke at the previous clock edge. n ote 2 . current state is defined as the state of the ddr3 sdram immediately prior to clock edge n . n ote 3 . c ommand ( n ) is the command registered at clock edge n , and action ( n ) is a result of c ommand ( n ), odt is not included here. n ote 4 . all states and sequences not shown are illegal or reserved unless explicitly descr ibed elsewhere in this document. n ote 5 . the state of odt does not affect the states described in this table. the odt function is not available during self - refresh. n ote 6 . during any cke transition (registration of cke h - >l or cke l - >h) the cke level must b e maintained until 1nck prior to tckemin being satisfied (at which time cke may transition again). n ote 7 . d eselect and nop are defined in the ? command truth table ? . n ote 8 . on s elf - r efres h e xit d eselect or nop commands must be issued on every clock edge occ urring during the txs period. read or odt commands may be issued only after txsdll is satisfied. n ote 9 . self - refresh mode can only be entered from the all banks idle state. n ote 10. must be a legal command as defined in the ? command truth table ? . n ote 11. va lid commands for p ower - d own e ntry and e xit are nop and d eselect only. n ote 12. valid commands for s elf - r efresh e xit are nop and d eselect only. n ote 13. self - refresh can not be entered d uring read or write operations. n ote 14. the power - down does not perform a ny refresh operations. n ote 15. ?x? means ?don?t care? (including floating around vref) in self - refresh and power - down. it also applies to address pins. n ote 16. vref (both v ref dq and v ref ca) must be maintained during self - refresh operation. v ref dq supply ma y be turned off and vrefdq may take any value between vss and vdd during self refresh
em4 7e m 32 8 8sba may. 201 2 27/ 37 www.eorex.com operation, provided that v ref dq is valid and stable prior to cke going back h igh and that first w rite operation or first w rite leveling a ctivity may not occur earlier tha n 512 nck after exit from self refresh. n ote 17. if all banks are closed at the conclusion of the read, write or precharge command, then precharge power - down is entered, otherwise active power - down is entered. n ote 18. ?idle state? is defined as all banks ar e closed (trp, tdal, etc. satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc.) as well as all s elf - r efresh exit and p ower - d own e xit parameters are satisfied (txs, txp, txpdll, etc).
em4 7e m 32 8 8sba may. 201 2 28/ 37 www.eorex.com initialization the following sequence is required for power - up and initialization and is shown in below figure: 1. apply power ( / reset is recommended to be maintained below 0.2 x vdd; all other inputs may be undefined) . / reset needs to be maintained for minimum 200 us with stable power. cke is pulled ?low? anytime before / reset being de - asserted (min. time 10 ns). the power voltage ramp time between 300 mv to vddmin must be no greater than 200 ms; and during the ramp, v dd > vddq and (vdd - vddq) < 0.3 volts. ? vdd and vddq are driven from a single power converter output, and ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or e qual to vssq and vss on the other side. in addition, vtt is limited to 0.95 v max once power ramp is finished, and ? vref tracks vddq/2. or ? apply vdd without any slope reversal before or at the same time as vddq. ? apply vddq without any slope reversal b efore or at the same time as vtt & vref. ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after / reset is de - asser ted, wait for another 500 us until cke becomes active. during this time, the dram will start internal state initialization; this will be done independently of external clocks. 3. clocks (ck, /c k) need to be started and stabilized for at least 10 ns or 5 t ck (which is larger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to clock (t is ) must be met. also, a nop or deselect command must be registered (with t is set up time to clock) before cke goes active. once the cke is registered ?high? after reset, cke needs to be continuously registered ?high? until the initialization sequence is finished, including expiration of t dllk and tzq init. 4. the ddr3 sdram keeps its on - die termination in high - impedance state as long as / r eset is asserted. further, the sdram keeps its on - die termination in h igh impedance state after / reset de- assertion until cke is registered high. the odt input signal may be in undefined state until t is before cke is registered high. when cke is registered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization sequence is finished, including the expiration of t dllk and t zq init. 5. after cke is being registered high, wait minimum of reset cke exit time, t xpr , before issuing the first mrs command to load mode register. (t xpr =max (t xs ; 5 x t ck ) 6. issue mrs command to load mr 2 with all application settings. (to issue mrs command for mr2 , provide ?low? to ba0 and ba2, ?high? to ba1.) 7. issue mrs command to load mr3 with all application settings. (to issue mrs command for mr3 , provide ?low? to ba2, ?high? to ba0 and ba1.) 8. is sue mrs command to load mr1 with all application settings and dll enabled. (to issue "dll enable"
em4 7e m 32 8 8sba may. 201 2 29/ 37 www.eorex.com command, provide "low" to a0, "high" to ba0 and "low" to ba1 ? ba2). 9. issue mrs command to load mr0 with all application settings and ?dll reset?. (to issue dll reset command, provide "high" to a8 and "low" to ba0 - 2). 10. issue zqcl command to starting zq calibration. 11. wait for both tdllk and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation. reset and power up initialization sequen ce
em4 7e m 32 8 8sba may. 201 2 30/ 37 www.eorex.com mode register definition mode register m r 0 the mode register mr0 stores the data for controlling various operating modes of ddr3 sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr and dll control for precharge power - down, which include various vendor specific options to make ddr3 sdram useful for various applications. the mode register is written by asserting low on / cs, / ras, / cas, / we, ba0, ba1 and ba2, while controlling the states of address pins according to the table below. 1 1 reserved 0 1 4 1 0 4 or 8 (otf) 0 0 8 a0 a1 bl 1 0 1 0 1 0 1 0 a4 0 1 1 11 0 1 1 10 0 0 1 9 0 0 1 8 0 1 0 7 0 1 0 6 0 0 0 reserved 0 0 0 reserved a2 a5 a6 cas latency 1 test 0 normal a7 mode 1 yes 0 no a8 dll reset 1 fast exit (dll on) 0 slow exit (dll off) a12 dll control (for precharge pd) 1 1 1 reserved 0 1 1 12 1 0 1 10 0 0 1 8 1 1 0 7 0 1 0 6 1 0 0 5 0 0 0 reserved a9 a10 a11 wr for autoprecharge 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode 1 interleave 0 nibble sequential a3 read burst type bl cl rbt cas latency tm dll wr ppd 0 0 0 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 1 1 reserved 0 1 4 1 0 4 or 8 (otf) 0 0 8 a0 a1 bl 1 0 1 0 1 0 1 0 a4 0 1 1 11 0 1 1 10 0 0 1 9 0 0 1 8 0 1 0 7 0 1 0 6 0 0 0 reserved 0 0 0 reserved a2 a5 a6 cas latency 1 test 0 normal a7 mode 1 yes 0 no a8 dll reset 1 fast exit (dll on) 0 slow exit (dll off) a12 dll control (for precharge pd) 1 1 1 reserved 0 1 1 12 1 0 1 10 0 0 1 8 1 1 0 7 0 1 0 6 1 0 0 5 0 0 0 reserved a9 a10 a11 wr for autoprecharge 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode 1 interleave 0 nibble sequential a3 read burst type bl cl rbt cas latency tm dll wr ppd 0 0 0 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 note1. ba2 and a13 are reserved for future use and must be programmed to 0 during mrs. note2. wr (write recovery for autoprecharge) min in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next in teger: wrmin[cycles] = roundup(t wr [ns]/t c k[ns]). the wr value in the mode register must be programmed to be equal or larger than wrmin. the programmed wr value is used with t rp to determine t dal .
em4 7e m 32 8 8sba may. 201 2 31/ 37 www.eorex.com burst type (a3) burst length r/w a2 a1 a0 sequential addressing , a3=0 interleave addressing , a3=1 4 (chop) r 0 0 0 0 1 2 3 t t t t 0 1 2 3 t t t t r 0 0 1 1 2 3 0 t t t t 1 0 3 2 t t t t r 0 1 0 2 3 0 1 t t t t 2 3 0 1 t t t t r 0 1 1 3 0 1 2 t t t t 3 2 1 0 t t t t r 1 0 0 4 5 6 7 t t t t 4 5 6 7 t t t t r 1 0 1 5 6 7 4 t t t t 5 4 7 6 t t t t r 1 1 0 6 7 4 5 t t t t 6 7 4 5 t t t t r 1 1 1 7 4 5 6 t t t t 7 6 5 4 t t t t w 0 v v 0 1 2 3 x x x x 0 1 2 3 x x x x w 1 v v 4 5 6 7 x x x x 4 5 6 7 x x x x 8 r 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 r 0 0 1 1 2 3 0 5 6 7 4 1 0 3 2 5 4 7 6 r 0 1 0 2 3 0 1 6 7 4 5 2 3 0 1 6 7 4 5 r 0 1 1 3 0 1 2 7 4 5 6 3 2 1 0 7 6 5 4 r 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 r 1 0 1 5 6 7 4 1 2 3 0 5 4 7 6 1 0 3 2 r 1 1 0 6 7 4 5 2 3 0 1 6 7 4 5 2 3 0 1 r 1 1 1 7 4 5 6 3 0 1 2 7 6 5 4 3 2 1 0 w v v v 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 note1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than for the bl8 mo de. this means that the starting point for twr and twtr will be pulled in by two clocks. in case of burst length being selected on - the - fly via a12 ( /bc ) , the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on- the - fly control, the starting point for twr and twtr will not be pulled in by two clocks. note2. 0...7 bit number is value of ca[2:0] that causes this bit to be the first read during a burst. note3. t: output driver for data and strobe s are in high impedance. note4. v: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. note5. x: don?t care.
em4 7e m 32 8 8sba may. 201 2 32/ 37 www.eorex.com cas latency the cas latency is defined by mr0 (bits a9 - a11) . cas latency is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. ddr3 sdram does not support any half - clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. test mode the normal operating mode is selected by mr0 (bit a7 = 0) and rest bits set to the desired values . programming bit a7 to a ?1? places the ddr3 sdram into a test mode that is only used by the dram factory and should not be used. no operations or functionality is speci fied if a7 = 1. dll reset the dll reset bit is self - clearing, meaning that it returns back to the value of ?0? after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. any time that the dll reset func tion is used, tdllk must be met before any functions that require the dll can be used (i.e., read commands or odt synchronous operations). write recovery the programmed wr value mr0 (bits a9, a10, and a11) is used for the auto precharge feature along with trp to determine tdal. wr (write recovery for auto - precharge) min in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer: wrmin[cycles] = roundup(twr[ns]/ tck[ns]). the wr must be programmed to be equal to or larger than twr(min). precharge pd dll mr0 (bit a12) is used to select the dll usage during precharge power - down mode. when mr0 (a12 = 0), or ?slow - exit?, the dll is frozen after entering precharge power - down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12 = 1), or ?fast - exit?, the dll is maintained after entering precharge power - down and upon exiting power - down requires txp to be met prior to the next valid command.
em4 7e m 32 8 8sba may. 201 2 33/ 37 www.eorex.com mode register mr1 the mode register mr1 stores the data for enabling or disabling the dll, output driver strength, rtt_nom impedance, additive latency, write leveling enable and qoff. the mode register 1 is written by asserting low on / cs, / ras, / cas, / we, high on ba0, lo w on ba1 and ba2, while controlling the states of address pins according to the table below. dll d.i.c rtt al d.i.c rtt level 0 rtt 0 0 qoff 0 0 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 1 disable 0 enable a0 dll enable 1 1 reserved 0 1 reserved 1 0 rzq/7 0 0 rzq/6 a1 a5 output driver impedance control 1 1 1 reserved 0 1 1 reserved 1 0 1 rzq/8 0 0 1 rzq/12 1 1 0 rzq/6 0 1 0 rzq/2 1 0 0 rzq/4 0 0 0 odt disabled a2 a6 a9 rtt_nom 1 output buffer disabled 0 output buffer enabled a12 qoff 1 1 reserved 0 1 cl - 2 1 0 cl - 1 0 0 al disabled a3 a4 additive latency 1 enabled 0 disabled a7 write leveling enable 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode dll d.i.c rtt al d.i.c rtt level 0 rtt 0 0 qoff 0 0 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 1 disable 0 enable a0 dll enable 1 1 reserved 0 1 reserved 1 0 rzq/7 0 0 rzq/6 a1 a5 output driver impedance control 1 1 1 reserved 0 1 1 reserved 1 0 1 rzq/8 0 0 1 rzq/12 1 1 0 rzq/6 0 1 0 rzq/2 1 0 0 rzq/4 0 0 0 odt disabled a2 a6 a9 rtt_nom 1 output buffer disabled 0 output buffer enabled a12 qoff 1 1 reserved 0 1 cl - 2 1 0 cl - 1 0 0 al disabled a3 a4 additive latency 1 enabled 0 disabled a7 write leveling enable 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode note1. ba2, a8, a10 and a13 are reserved for future use (rfu) and must be programmed to 0 during mrs. note2. qoff: outputs disabled - dqs, dqss, / dqss. note3. i n write leveling mode ( mr1 [bit7] = 1) with mr1 [bit12] = 1, all rtt_nom settings are allowed; in write leveling mode ( mr1 [bit7] = 1) with mr1 [bit12] = 0, only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. dll enable the dll must be enabled for no rmal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. during normal operation (dll - on) with mr1 (a0 = 0), the dll is automatically disabled when entering s elf - r efresh op eration and is automatically re - enabled upon exit of s elf - r efresh operation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a r ead or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not require dll for any write oper ation, except when rtt_wr is enabled and the dll is required for
em4 7e m 32 8 8sba may. 201 2 34/ 37 www.eorex.com proper odt operation. for more detailed information on dll disable operation refers to ?dll - off mode? . the direct odt feature is not supported during dll - off mode. the on - die termination res istors must be disabled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1 {a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2 {a10, a9} = {0,0}, to disable dynamic odt externally. odt rtt values ddr3 sdram is capable of providing two different termination values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmed in mr1 . a sep arate value (rtt_wr) may be programmed in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied during writes even when rtt_nom is disabled. additive latency additive latency (al) operation is supported to make command and data bus efficient for sustainable bandwidths in ddr3 sdram. in this operation, i t allows a read or write command (either with or without auto - precharge) to be issued immediately after the active command. the command is held for the time of th e additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register setti ngs. write leveling for better signal integrity, ddr3 memory module adopted fly - by topology for the commands, addresses, control signals, and clocks. the fly - by topology has the benefit of reducing the number of stubs and their length, but it also causes f light time skew between clock and strobe at every dram on the dimm. this makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the ddr3 sdram supports a ?write leveling? feature to allow the controller to compens ate for skew. output disable the outputs may be en abled/disabled by mr1 (bit a12) . when this feature is enabled (a12 = 1), all output pins (dqs, dqs, / dqs, etc.) are disconnected from the device, thus removing any loading of the output drivers. for normal operation, a12 should be set to ?0?.
em4 7e m 32 8 8sba may. 201 2 35/ 37 www.eorex.com mode register mr2 the mode register mr2 stores the data for controlling refresh related features, including rtt_wr impedance and cas write latency (cwl). the mode register 2 is written by asserting low on / cs, / ras, / cas, / we, high on ba1, low on ba0 and ba2, while controlling the states of address pins according to the table below. 0 cwl 0 srt 0 rtt_wr 0 0 0 0 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 1 1 1 reserved 0 1 1 reserved 1 0 1 reserved 0 0 1 reserved 1 1 0 8 (1.5ns t ck R 1 .25ns) 0 1 0 7 (1.875ns t ck R 1 .5ns) 1 0 0 6 (2.5ns t ck R 1 .875ns) 0 0 0 5( t ck R 2.5 ns) a3 a4 a6 cas write latency (cwl) 1 extended temp. self refresh 0 normal operating temp. range a7 self refresh temp. range 1 1 reserved 0 1 rzq/2 1 0 rzq/4 0 0 dynamic odt off a9 a10 rtt_wr 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode 0 cwl 0 srt 0 rtt_wr 0 0 0 0 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 1 1 1 reserved 0 1 1 reserved 1 0 1 reserved 0 0 1 reserved 1 1 0 8 (1.5ns t ck R 1 .25ns) 0 1 0 7 (1.875ns t ck R 1 .5ns) 1 0 0 6 (2.5ns t ck R 1 .875ns) 0 0 0 5( t ck R 2.5 ns) a3 a4 a6 cas write latency (cwl) 1 extended temp. self refresh 0 normal operating temp. range a7 self refresh temp. range 1 1 reserved 0 1 rzq/2 1 0 rzq/4 0 0 dynamic odt off a9 a10 rtt_wr 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode note1. ba2, a8, a11 ~ a13 are rfu and must be programmed to 0 during mrs. note2. the rtt_wr value can be applied during writes even whe n rtt_nom is disabled. during write leveling, dynamic odt is not available. cas write latency (cwl) the cas write latency is defined by mr2 (bits a3 - a5). cas write latency is the delay, in clock cycles, between the internal write command and the availabili ty of the first bit of input data. ddr3 sdram does not support any half - clock latencies. the overall write latency (wl) is defined as additive latency (al) + cas write latency (cwl); wl = al + cwl. dynamic odt (rtt_wr) ddr3 sdram introduces a new feature ? dynamic odt?. in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure t he dynamic odt set t ings. in write leveling m ode, only rtt_nom is available.
em4 7e m 32 8 8sba may. 201 2 36/ 37 www.eorex.com mode register mr3 the mode register mr3 controls multi purpose registers (mpr). the mode register 3 is written by asserting low on cs, ras, cas, we, high on ba1 and ba0, and low o n ba2 while controlling the states of address pins according to the table below. mpr location mpr 0 0 0 0 0 0 0 0 0 0 0 1 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode 1 1 reserved 0 1 reserved 1 0 reserved 0 0 predefined pattern a0 a1 mpr location 1 dataflow from mpr 0 normal operation a2 mpr operation mpr location mpr 0 0 0 0 0 0 0 0 0 0 0 1 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 1 1 mr3 0 1 mr2 1 0 mr1 0 0 mr0 ba0 ba1 mrs mode 1 1 reserved 0 1 reserved 1 0 reserved 0 0 predefined pattern a0 a1 mpr location 1 dataflow from mpr 0 normal operation a2 mpr operation note1. ba2, a3 - a13 are reserved for future use (rfu) and must be programmed to 0 during mrs. note2. the predefined pattern will be used for read synchronization. note3. wh en mpr control is set for normal operation, mr3 a[2] = 0, mr3 a[1:0] will be ignored multi purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. to enable the mpr, a mode r egister set (mrs) command must be issued to mr3 register with bit a2 = 1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirecte d to the multi purpose register. when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled ( mr3 bit a2 = 0). power - d own mode, s elf - r efresh and any other non- rd/rda command is not allowed dur ing mpr enable mode. the reset function is supported during mpr enable mode.
em4 7e m 32 8 8sba may. 201 2 37/ 37 www.eorex.com package description : 136 ball - fbga solder ball: lead free (sn - ag - cu) a b c d e f g h j k l m n p r t u 12 11 10 9 8 7 6 5 4 3 2 1 8.8 unit: mm 0.80 14.0 0.1 a1 12.0 0.1 12.8 1.6 1.4 max 0.45 0.05 0.15 max 0.98 0.80 0.6

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